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<div class="title">xmipi_tx_phy_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga6bd9c3f2f20cf79b7bd8a52a67b36467"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga6bd9c3f2f20cf79b7bd8a52a67b36467">XMIPI_TX_PHY_HW_H_</a></td></tr>
<tr class="memdesc:ga6bd9c3f2f20cf79b7bd8a52a67b36467"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="group__mipi__tx__phy.html#ga6bd9c3f2f20cf79b7bd8a52a67b36467">More...</a><br/></td></tr>
<tr class="separator:ga6bd9c3f2f20cf79b7bd8a52a67b36467"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register sets of MIPI_TX_PHY </p>
</div></td></tr>
<tr class="memitem:gabbf8c59ccf6c1abcef8dd1c7cb06473c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gabbf8c59ccf6c1abcef8dd1c7cb06473c">XMIPI_TX_PHY_CTRL_REG_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:gabbf8c59ccf6c1abcef8dd1c7cb06473c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="group__mipi__tx__phy.html#gabbf8c59ccf6c1abcef8dd1c7cb06473c">More...</a><br/></td></tr>
<tr class="separator:gabbf8c59ccf6c1abcef8dd1c7cb06473c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e16ded337e70f28b3ba7c3c791f736a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga6e16ded337e70f28b3ba7c3c791f736a">XMIPI_TX_PHY_VERSION_REG_OFFSET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga6e16ded337e70f28b3ba7c3c791f736a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Version Register.  <a href="group__mipi__tx__phy.html#ga6e16ded337e70f28b3ba7c3c791f736a">More...</a><br/></td></tr>
<tr class="separator:ga6e16ded337e70f28b3ba7c3c791f736a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga06d4f400a133fadb577204eb236d8b60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga06d4f400a133fadb577204eb236d8b60">XMIPI_TX_PHY_INIT_TIMER_REG_OFFSET</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga06d4f400a133fadb577204eb236d8b60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialization Timer Register.  <a href="group__mipi__tx__phy.html#ga06d4f400a133fadb577204eb236d8b60">More...</a><br/></td></tr>
<tr class="separator:ga06d4f400a133fadb577204eb236d8b60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38135baf5eb6b624dacae2760a87f276"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga38135baf5eb6b624dacae2760a87f276">XMIPI_TX_PHY_HSTIMEOUT_REG_OFFSET</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga38135baf5eb6b624dacae2760a87f276"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog timeout in HS mode Register.  <a href="group__mipi__tx__phy.html#ga38135baf5eb6b624dacae2760a87f276">More...</a><br/></td></tr>
<tr class="separator:ga38135baf5eb6b624dacae2760a87f276"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3dd41b223fba7f1f0c099f9444944b19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga3dd41b223fba7f1f0c099f9444944b19">XMIPI_TX_PHY_ESCTIMEOUT_REG_OFFSET</a>&#160;&#160;&#160;0x00000014</td></tr>
<tr class="memdesc:ga3dd41b223fba7f1f0c099f9444944b19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Goto Stop state on timeout timer Register.  <a href="group__mipi__tx__phy.html#ga3dd41b223fba7f1f0c099f9444944b19">More...</a><br/></td></tr>
<tr class="separator:ga3dd41b223fba7f1f0c099f9444944b19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee3555d2cc9dc91c2f13f39f246af4ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaee3555d2cc9dc91c2f13f39f246af4ac">XMIPI_TX_PHY_CLSTATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:gaee3555d2cc9dc91c2f13f39f246af4ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clk lane PHY error Status Register.  <a href="group__mipi__tx__phy.html#gaee3555d2cc9dc91c2f13f39f246af4ac">More...</a><br/></td></tr>
<tr class="separator:gaee3555d2cc9dc91c2f13f39f246af4ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77c981eb784b931ddee9637d03dfafa6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga77c981eb784b931ddee9637d03dfafa6">XMIPI_TX_PHY_DL0STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x0000001C</td></tr>
<tr class="memdesc:ga77c981eb784b931ddee9637d03dfafa6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 0 PHY error Status Register.  <a href="group__mipi__tx__phy.html#ga77c981eb784b931ddee9637d03dfafa6">More...</a><br/></td></tr>
<tr class="separator:ga77c981eb784b931ddee9637d03dfafa6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16d4d03a4897453d51733d12036c3b02"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga16d4d03a4897453d51733d12036c3b02">XMIPI_TX_PHY_DL1STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga16d4d03a4897453d51733d12036c3b02"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 1 PHY error Status Register.  <a href="group__mipi__tx__phy.html#ga16d4d03a4897453d51733d12036c3b02">More...</a><br/></td></tr>
<tr class="separator:ga16d4d03a4897453d51733d12036c3b02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf23b1a894f2241c14d64c555f90a7447"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaf23b1a894f2241c14d64c555f90a7447">XMIPI_TX_PHY_DL2STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000024</td></tr>
<tr class="memdesc:gaf23b1a894f2241c14d64c555f90a7447"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 2 PHY error Status Register.  <a href="group__mipi__tx__phy.html#gaf23b1a894f2241c14d64c555f90a7447">More...</a><br/></td></tr>
<tr class="separator:gaf23b1a894f2241c14d64c555f90a7447"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79aad6bfa8e6ae4383887cb10eeb7ef8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga79aad6bfa8e6ae4383887cb10eeb7ef8">XMIPI_TX_PHY_DL3STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000028</td></tr>
<tr class="memdesc:ga79aad6bfa8e6ae4383887cb10eeb7ef8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 3 PHY error Status Register.  <a href="group__mipi__tx__phy.html#ga79aad6bfa8e6ae4383887cb10eeb7ef8">More...</a><br/></td></tr>
<tr class="separator:ga79aad6bfa8e6ae4383887cb10eeb7ef8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga595261095922dacb175e9b163bd5f31b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga595261095922dacb175e9b163bd5f31b">XMIPI_TX_PHY_PROG_SEQ_CTRL_OFFSET</a>&#160;&#160;&#160;0x00000038</td></tr>
<tr class="memdesc:ga595261095922dacb175e9b163bd5f31b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prog Seq Control Register.  <a href="group__mipi__tx__phy.html#ga595261095922dacb175e9b163bd5f31b">More...</a><br/></td></tr>
<tr class="separator:ga595261095922dacb175e9b163bd5f31b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab4e89fb7aee1d0061973313026d5e6cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gab4e89fb7aee1d0061973313026d5e6cd">XMIPI_TX_PHY_PROG_SEQ_DATA0_OFFSET</a>&#160;&#160;&#160;0x0000003C</td></tr>
<tr class="memdesc:gab4e89fb7aee1d0061973313026d5e6cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prog Seq Data Register 0.  <a href="group__mipi__tx__phy.html#gab4e89fb7aee1d0061973313026d5e6cd">More...</a><br/></td></tr>
<tr class="separator:gab4e89fb7aee1d0061973313026d5e6cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7de26ed0365215b08af78324dfb3550b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga7de26ed0365215b08af78324dfb3550b">XMIPI_TX_PHY_PROG_SEQ_DATA1_OFFSET</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga7de26ed0365215b08af78324dfb3550b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prog Seq Data Register 1.  <a href="group__mipi__tx__phy.html#ga7de26ed0365215b08af78324dfb3550b">More...</a><br/></td></tr>
<tr class="separator:ga7de26ed0365215b08af78324dfb3550b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XMIPI_TX_PHY_CTRL_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used for the enabling/disabling and resetting the MIPI_TX_PHY </p>
</div></td></tr>
<tr class="memitem:gaff7758fee41117064aa8d27b5ee69de7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaff7758fee41117064aa8d27b5ee69de7">XMIPI_TX_PHY_CTRL_REG_SOFTRESET_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaff7758fee41117064aa8d27b5ee69de7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Soft Reset.  <a href="group__mipi__tx__phy.html#gaff7758fee41117064aa8d27b5ee69de7">More...</a><br/></td></tr>
<tr class="separator:gaff7758fee41117064aa8d27b5ee69de7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8340e846c67ddfc75a11bbd4ac5269d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gae8340e846c67ddfc75a11bbd4ac5269d">XMIPI_TX_PHY_CTRL_REG_PHYEN_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gae8340e846c67ddfc75a11bbd4ac5269d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable controller.  <a href="group__mipi__tx__phy.html#gae8340e846c67ddfc75a11bbd4ac5269d">More...</a><br/></td></tr>
<tr class="separator:gae8340e846c67ddfc75a11bbd4ac5269d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab53fbae94c162e2810f2e8bc4d19130"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaab53fbae94c162e2810f2e8bc4d19130">XMIPI_TX_PHY_CTRL_REG_SOFTRESET_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gaab53fbae94c162e2810f2e8bc4d19130"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Soft Reset.  <a href="group__mipi__tx__phy.html#gaab53fbae94c162e2810f2e8bc4d19130">More...</a><br/></td></tr>
<tr class="separator:gaab53fbae94c162e2810f2e8bc4d19130"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba9c09bed36f1c618981e53063651f68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaba9c09bed36f1c618981e53063651f68">XMIPI_TX_PHY_CTRL_REG_PHYEN_OFFSET</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gaba9c09bed36f1c618981e53063651f68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for PHY Enable.  <a href="group__mipi__tx__phy.html#gaba9c09bed36f1c618981e53063651f68">More...</a><br/></td></tr>
<tr class="separator:gaba9c09bed36f1c618981e53063651f68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1eb36a3a4dac7d8bb40282fc26f16f35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga1eb36a3a4dac7d8bb40282fc26f16f35">XMIPI_TX_PHY_PROG_SEQ_EN_MASK</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:ga1eb36a3a4dac7d8bb40282fc26f16f35"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable Prog Seq.  <a href="group__mipi__tx__phy.html#ga1eb36a3a4dac7d8bb40282fc26f16f35">More...</a><br/></td></tr>
<tr class="separator:ga1eb36a3a4dac7d8bb40282fc26f16f35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XMIPI_TX_PHY_INIT_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used for lane Initialization.</p>
<p>Recommended to use 1ms or longer in for TX mode and 200us-500us for RX mode </p>
</div></td></tr>
<tr class="memitem:gaf73370659b96757f31e43b0b82e6cc80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaf73370659b96757f31e43b0b82e6cc80">XMIPI_TX_PHY_INIT_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:gaf73370659b96757f31e43b0b82e6cc80"><td class="mdescLeft">&#160;</td><td class="mdescRight">Init Timer value in ns.  <a href="group__mipi__tx__phy.html#gaf73370659b96757f31e43b0b82e6cc80">More...</a><br/></td></tr>
<tr class="separator:gaf73370659b96757f31e43b0b82e6cc80"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga08167d1c5a8c66e26d2dbf0728f64be6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga08167d1c5a8c66e26d2dbf0728f64be6">XMIPI_TX_PHY_INIT_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga08167d1c5a8c66e26d2dbf0728f64be6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Init Timer.  <a href="group__mipi__tx__phy.html#ga08167d1c5a8c66e26d2dbf0728f64be6">More...</a><br/></td></tr>
<tr class="separator:ga08167d1c5a8c66e26d2dbf0728f64be6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XMIPI_TX_PHY_HSTIMEOUT_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to program watchdog timer in high speed mode.</p>
<p>Default value is 65541. Valid range 1000-65541. </p>
</div></td></tr>
<tr class="memitem:gad649853612197175df11883ab64abe41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gad649853612197175df11883ab64abe41">XMIPI_TX_PHY_HSTIMEOUT_REG_TIMEOUT_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:gad649853612197175df11883ab64abe41"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_TX_TIMEOUT Received.  <a href="group__mipi__tx__phy.html#gad649853612197175df11883ab64abe41">More...</a><br/></td></tr>
<tr class="separator:gad649853612197175df11883ab64abe41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga002f9c985356152a355bc1f44b021366"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga002f9c985356152a355bc1f44b021366">XMIPI_TX_PHY_HSTIMEOUT_REG_TIMEOUT_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga002f9c985356152a355bc1f44b021366"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Timeout.  <a href="group__mipi__tx__phy.html#ga002f9c985356152a355bc1f44b021366">More...</a><br/></td></tr>
<tr class="separator:ga002f9c985356152a355bc1f44b021366"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XMIPI_TX_PHY_ESCTIMEOUT_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains Rx Data Lanes timeout for watchdog timer in escape mode. </p>
</div></td></tr>
<tr class="memitem:ga3b3542421ec553cab65cbdb1145b146a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga3b3542421ec553cab65cbdb1145b146a">XMIPI_TX_PHY_ESCTIMEOUT_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga3b3542421ec553cab65cbdb1145b146a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Escape Timout Value.  <a href="group__mipi__tx__phy.html#ga3b3542421ec553cab65cbdb1145b146a">More...</a><br/></td></tr>
<tr class="separator:ga3b3542421ec553cab65cbdb1145b146a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1b47a9cfeecf567a00b6ae5e3b1ae55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaf1b47a9cfeecf567a00b6ae5e3b1ae55">XMIPI_TX_PHY_ESCTIMEOUT_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gaf1b47a9cfeecf567a00b6ae5e3b1ae55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Escape Timeout.  <a href="group__mipi__tx__phy.html#gaf1b47a9cfeecf567a00b6ae5e3b1ae55">More...</a><br/></td></tr>
<tr class="separator:gaf1b47a9cfeecf567a00b6ae5e3b1ae55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XMIPI_TX_PHY_CLSTATUS_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the clock lane status and state machine control. </p>
</div></td></tr>
<tr class="memitem:ga89763534a7c4bbbb64696d34d35df25c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga89763534a7c4bbbb64696d34d35df25c">XMIPI_TX_PHY_CLSTATUS_REG_ERRCTRL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga89763534a7c4bbbb64696d34d35df25c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock lane control error.  <a href="group__mipi__tx__phy.html#ga89763534a7c4bbbb64696d34d35df25c">More...</a><br/></td></tr>
<tr class="separator:ga89763534a7c4bbbb64696d34d35df25c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9bcfcbfc2bc59101377b603ee65b87ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga9bcfcbfc2bc59101377b603ee65b87ae">XMIPI_TX_PHY_CLSTATUS_REG_STOPSTATE_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga9bcfcbfc2bc59101377b603ee65b87ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock lane stop state.  <a href="group__mipi__tx__phy.html#ga9bcfcbfc2bc59101377b603ee65b87ae">More...</a><br/></td></tr>
<tr class="separator:ga9bcfcbfc2bc59101377b603ee65b87ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b1c1cac54af04e31c36599ed6e8062a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga2b1c1cac54af04e31c36599ed6e8062a">XMIPI_TX_PHY_CLSTATUS_REG_INITDONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga2b1c1cac54af04e31c36599ed6e8062a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialization done bit.  <a href="group__mipi__tx__phy.html#ga2b1c1cac54af04e31c36599ed6e8062a">More...</a><br/></td></tr>
<tr class="separator:ga2b1c1cac54af04e31c36599ed6e8062a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6aece57daaccf4f982fddf764b15a868"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga6aece57daaccf4f982fddf764b15a868">XMIPI_TX_PHY_CLSTATUS_REG_ULPS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga6aece57daaccf4f982fddf764b15a868"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set in ULPS mode.  <a href="group__mipi__tx__phy.html#ga6aece57daaccf4f982fddf764b15a868">More...</a><br/></td></tr>
<tr class="separator:ga6aece57daaccf4f982fddf764b15a868"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec485fecc0d01a6803f437395cc66f5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaec485fecc0d01a6803f437395cc66f5b">XMIPI_TX_PHY_CLSTATUS_REG_MODE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:gaec485fecc0d01a6803f437395cc66f5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Low, High, Esc mode.  <a href="group__mipi__tx__phy.html#gaec485fecc0d01a6803f437395cc66f5b">More...</a><br/></td></tr>
<tr class="separator:gaec485fecc0d01a6803f437395cc66f5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ec9bd18504fe7f5dacbc1bf777d1924"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0ec9bd18504fe7f5dacbc1bf777d1924"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_TX_PHY_CLSTATUS_ALLMASK</b></td></tr>
<tr class="separator:ga0ec9bd18504fe7f5dacbc1bf777d1924"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17528c58e673adc82f62fbeab06b22b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga17528c58e673adc82f62fbeab06b22b8">XMIPI_TX_PHY_CLSTATUS_REG_ERRCTRL_OFFSET</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga17528c58e673adc82f62fbeab06b22b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Control Error on Clock.  <a href="group__mipi__tx__phy.html#ga17528c58e673adc82f62fbeab06b22b8">More...</a><br/></td></tr>
<tr class="separator:ga17528c58e673adc82f62fbeab06b22b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f13683048291c23c8a62cb99de4159a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga9f13683048291c23c8a62cb99de4159a">XMIPI_TX_PHY_CLSTATUS_REG_STOPSTATE_OFFSET</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga9f13683048291c23c8a62cb99de4159a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Stop State on Clock.  <a href="group__mipi__tx__phy.html#ga9f13683048291c23c8a62cb99de4159a">More...</a><br/></td></tr>
<tr class="separator:ga9f13683048291c23c8a62cb99de4159a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace4f962db90a3d55720867e7e0eb81cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gace4f962db90a3d55720867e7e0eb81cc">XMIPI_TX_PHY_CLSTATUS_REG_INITDONE_OFFSET</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gace4f962db90a3d55720867e7e0eb81cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Initialization Done.  <a href="group__mipi__tx__phy.html#gace4f962db90a3d55720867e7e0eb81cc">More...</a><br/></td></tr>
<tr class="separator:gace4f962db90a3d55720867e7e0eb81cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3ad7fcdb85bb50e61fccaa519274bd6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga3ad7fcdb85bb50e61fccaa519274bd6f">XMIPI_TX_PHY_CLSTATUS_REG_ULPS_OFFSET</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga3ad7fcdb85bb50e61fccaa519274bd6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for ULPS.  <a href="group__mipi__tx__phy.html#ga3ad7fcdb85bb50e61fccaa519274bd6f">More...</a><br/></td></tr>
<tr class="separator:ga3ad7fcdb85bb50e61fccaa519274bd6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8444ef3ccc6b6a472a6393fd5326027e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga8444ef3ccc6b6a472a6393fd5326027e">XMIPI_TX_PHY_CLSTATUS_REG_MODE_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga8444ef3ccc6b6a472a6393fd5326027e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Mode bits.  <a href="group__mipi__tx__phy.html#ga8444ef3ccc6b6a472a6393fd5326027e">More...</a><br/></td></tr>
<tr class="separator:ga8444ef3ccc6b6a472a6393fd5326027e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XMIPI_TX_PHY_DLxSTATUS_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the data lanes status </p>
</div></td></tr>
<tr class="memitem:ga37f17efe16bf0d8be132b6e0619a341e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga37f17efe16bf0d8be132b6e0619a341e">XMIPI_TX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga37f17efe16bf0d8be132b6e0619a341e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Count.  <a href="group__mipi__tx__phy.html#ga37f17efe16bf0d8be132b6e0619a341e">More...</a><br/></td></tr>
<tr class="separator:ga37f17efe16bf0d8be132b6e0619a341e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac00ba9ecef3361a5bb9fcf0e20a9c6e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gac00ba9ecef3361a5bb9fcf0e20a9c6e6">XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:gac00ba9ecef3361a5bb9fcf0e20a9c6e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calib status.  <a href="group__mipi__tx__phy.html#gac00ba9ecef3361a5bb9fcf0e20a9c6e6">More...</a><br/></td></tr>
<tr class="separator:gac00ba9ecef3361a5bb9fcf0e20a9c6e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabcf51a2a9b4602aa06828c55b7fef9d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gabcf51a2a9b4602aa06828c55b7fef9d4">XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gabcf51a2a9b4602aa06828c55b7fef9d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calib complete.  <a href="group__mipi__tx__phy.html#gabcf51a2a9b4602aa06828c55b7fef9d4">More...</a><br/></td></tr>
<tr class="separator:gabcf51a2a9b4602aa06828c55b7fef9d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f65a8dea651af7702362ae7ef30e191"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga6f65a8dea651af7702362ae7ef30e191">XMIPI_TX_PHY_DLXSTATUS_REG_STOP_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga6f65a8dea651af7702362ae7ef30e191"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop State on data lane.  <a href="group__mipi__tx__phy.html#ga6f65a8dea651af7702362ae7ef30e191">More...</a><br/></td></tr>
<tr class="separator:ga6f65a8dea651af7702362ae7ef30e191"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad128be776c9344fcec21c7ad7579a2c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gad128be776c9344fcec21c7ad7579a2c1">XMIPI_TX_PHY_DLXSTATUS_REG_ESCABRT_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gad128be776c9344fcec21c7ad7579a2c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set on Data Lane Esc timeout occurs.  <a href="group__mipi__tx__phy.html#gad128be776c9344fcec21c7ad7579a2c1">More...</a><br/></td></tr>
<tr class="separator:gad128be776c9344fcec21c7ad7579a2c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga54d606cb5490a7e1dd6f2f123c028833"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga54d606cb5490a7e1dd6f2f123c028833">XMIPI_TX_PHY_DLXSTATUS_REG_HSABRT_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga54d606cb5490a7e1dd6f2f123c028833"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set on Data Lane HS timeout.  <a href="group__mipi__tx__phy.html#ga54d606cb5490a7e1dd6f2f123c028833">More...</a><br/></td></tr>
<tr class="separator:ga54d606cb5490a7e1dd6f2f123c028833"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga65aea4fb42069d3515c6667c03b90804"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga65aea4fb42069d3515c6667c03b90804">XMIPI_TX_PHY_DLXSTATUS_REG_INITDONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga65aea4fb42069d3515c6667c03b90804"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set after initialization.  <a href="group__mipi__tx__phy.html#ga65aea4fb42069d3515c6667c03b90804">More...</a><br/></td></tr>
<tr class="separator:ga65aea4fb42069d3515c6667c03b90804"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9a2034abf3cea4fd0d702dc9d364ff0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaf9a2034abf3cea4fd0d702dc9d364ff0">XMIPI_TX_PHY_DLXSTATUS_REG_ULPS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaf9a2034abf3cea4fd0d702dc9d364ff0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set when MIPI_TX_PHY in ULPS mode.  <a href="group__mipi__tx__phy.html#gaf9a2034abf3cea4fd0d702dc9d364ff0">More...</a><br/></td></tr>
<tr class="separator:gaf9a2034abf3cea4fd0d702dc9d364ff0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5bf3d01103d08acc8bbb1cf2cb80ef4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gab5bf3d01103d08acc8bbb1cf2cb80ef4">XMIPI_TX_PHY_DLXSTATUS_REG_MODE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:gab5bf3d01103d08acc8bbb1cf2cb80ef4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Mode (Esc, Low, High) of Data Lane.  <a href="group__mipi__tx__phy.html#gab5bf3d01103d08acc8bbb1cf2cb80ef4">More...</a><br/></td></tr>
<tr class="separator:gab5bf3d01103d08acc8bbb1cf2cb80ef4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga35fe51d4fe33d10564b2676597896aa5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga35fe51d4fe33d10564b2676597896aa5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_TX_PHY_DLXSTATUS_ALLMASK</b></td></tr>
<tr class="separator:ga35fe51d4fe33d10564b2676597896aa5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabfa6f4bbcae507932db411474983c466"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gabfa6f4bbcae507932db411474983c466">XMIPI_TX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gabfa6f4bbcae507932db411474983c466"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset packet count.  <a href="group__mipi__tx__phy.html#gabfa6f4bbcae507932db411474983c466">More...</a><br/></td></tr>
<tr class="separator:gabfa6f4bbcae507932db411474983c466"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb2c29072f2f4470428afb2b2fb66e28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaeb2c29072f2f4470428afb2b2fb66e28">XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gaeb2c29072f2f4470428afb2b2fb66e28"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset calib status.  <a href="group__mipi__tx__phy.html#gaeb2c29072f2f4470428afb2b2fb66e28">More...</a><br/></td></tr>
<tr class="separator:gaeb2c29072f2f4470428afb2b2fb66e28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga28466e4ed8a8e07b00371f6e6062189b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga28466e4ed8a8e07b00371f6e6062189b">XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:ga28466e4ed8a8e07b00371f6e6062189b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset Calib complete.  <a href="group__mipi__tx__phy.html#ga28466e4ed8a8e07b00371f6e6062189b">More...</a><br/></td></tr>
<tr class="separator:ga28466e4ed8a8e07b00371f6e6062189b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4802b5075a9ba293b4c0f3ba76d46905"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga4802b5075a9ba293b4c0f3ba76d46905">XMIPI_TX_PHY_DLXSTATUS_REG_STOP_OFFSET</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga4802b5075a9ba293b4c0f3ba76d46905"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Stop State.  <a href="group__mipi__tx__phy.html#ga4802b5075a9ba293b4c0f3ba76d46905">More...</a><br/></td></tr>
<tr class="separator:ga4802b5075a9ba293b4c0f3ba76d46905"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga78e9d7fe89467eb850509947b1695619"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga78e9d7fe89467eb850509947b1695619">XMIPI_TX_PHY_DLXSTATUS_REG_ESCABRT_OFFSET</a>&#160;&#160;&#160;5</td></tr>
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<tr class="memitem:gacfe5c375a23a599452314f778b88cf94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gacfe5c375a23a599452314f778b88cf94">XMIPI_TX_PHY_DLXSTATUS_REG_HSABRT_OFFSET</a>&#160;&#160;&#160;4</td></tr>
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<tr class="memitem:ga4d4bf96f1ff599cf39682ae6f7733369"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga4d4bf96f1ff599cf39682ae6f7733369">XMIPI_TX_PHY_DLXSTATUS_REG_MODE_OFFSET</a>&#160;&#160;&#160;0</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XMIPI_TX_PHY_HSSETTLE_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to program the HS SETTLE register.</p>
<p>Default value is 135 + 10UI. </p>
</div></td></tr>
<tr class="memitem:gadd2ac13ad244c63767708f50754e91eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gadd2ac13ad244c63767708f50754e91eb">XMIPI_TX_PHY_HSSETTLE_REG_TIMEOUT_MASK</a>&#160;&#160;&#160;0x1FF</td></tr>
<tr class="memdesc:gadd2ac13ad244c63767708f50754e91eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_SETTLE value.  <a href="group__mipi__tx__phy.html#gadd2ac13ad244c63767708f50754e91eb">More...</a><br/></td></tr>
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<tr class="memitem:ga288b6d3f90fa63aa3d6ea45d19e12746"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga288b6d3f90fa63aa3d6ea45d19e12746">XMIPI_TX_PHY_HSSETTLE_REG_TIMEOUT_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga288b6d3f90fa63aa3d6ea45d19e12746"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for HS_SETTLE.  <a href="group__mipi__tx__phy.html#ga288b6d3f90fa63aa3d6ea45d19e12746">More...</a><br/></td></tr>
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